A forward body-biased low-leakage SRAM cache: Device, circuit and architecture considerations
- Chris Hyung-Il Kim
- Jae-Joon Kim
- et al.
- 2005
- IEEE Transactions on VLSI Systems
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45 results for Kaushik Roy
Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET's
- Chris H. Kim
- Hari Ananthan
- et al.
- 2004
- IEEE International SOI Conference 2004
Double gate-MOSFET subthreshold circuit for ultralow power applications
- Jae-Joon Kim
- Kaushik Roy
- 2004
- IEEE Transactions on Electron Devices
SOI-optimized 64-bit high-speed CMOS adder design
- Jae-Joon Kim
- Rajiv Joshi
- et al.
- 2002
- VLSI Circuits 2002
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
- Prithviraj Banerjee
- Joe T. Rahmeh
- et al.
- 1990
- IEEE TC