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3D chip-stacking technology with through-silicon vias and low-volume lead free interconnectionsKatsuyuki SakumaPaul S. Andryet al.2008IBM J. Res. Dev
3D chip stacking technology with low-volume lead-free interconnectionsK. SakumaP. Andryet al.2007ECTC 2007
Assembly, characterization, and reworkability of Pb-free ultra-fine pitch C4s for system-on-packageB. DangS.L. Wrightet al.2007ECTC 2007
Pb-free micro-joints (50 μm pitch) for the next generation micro-systems: The fabrication, assembly and characterizationH. GanS.L. Wrightet al.2006ECTC 2006
System-on-Package (SOP) technology, characterization and applicationsJ. KnickerbockerP. Andryet al.2006ECTC 2006
A CMOS-compatible process for fabricating electrical through-vias in siliconP. AndryC. Tsanget al.2006ECTC 2006