Matrix-matrix multiplication on a large register file architecture with indirection
- Dheeraj Sreedhar
- J.H. Derby
- et al.
- 2014
- HiPC 2014
Conference paper
Publications
10 results for C.L. Johnson
Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure
- D. Sreedhar
- J.H. Derby
- et al.
- 2013
- ICASSP 2013
Conference paperThrough silicon via aware design planning for thermally efficient 3-D integrated circuits
- Yibo Chen
- Eren Kursun
- et al.
- 2013
- IEEE TCADIS
PaperArchitectural perspectives of future wireless base stations based on the IBM PowerEN™ processor
- Augusto Vega
- Pradip Bose
- et al.
- 2012
- HPCA 2012
Conference paperAnalysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
- Yibo Chen
- Eren Kursun
- et al.
- 2011
- ISLPED 2011
Conference paperEarly chip planning cockpit
- Jeonghee Shin
- John A. Darringer
- et al.
- 2011
- DATE 2011
Conference paperA wire-speed power™ processor: 2.3GHz 45nm SOI with 16 cores and 64 threads
- Charles Johnson
- David H. Allen
- et al.
- 2010
- ISSCC 2010
Conference paperWorkload and network-optimized computing systems
- D.P. LaPotin
- Shahrokh Daijavad
- et al.
- 2010
- IBM J. Res. Dev
PaperIntroduction to the wire-speed processor and architecture
- Hubertus Franke
- Jimi Xenidis
- et al.
- 2010
- IBM J. Res. Dev
PaperFuture processors: Flexible and modular
- Charlie Johnson
- Jeff Welser
- 2005
- CODES - ISSS 2005
Conference paper