Toward ultimate scaling of MOSFET
- Ramachandran Muralidhar
- Isaac Lauer
- et al.
- 2016
- IEEE T-ED
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37 results for Isaac Lauer
Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond
- Seong-Dong Kim
- Michael Guillorn
- et al.
- 2015
- S3S 2015
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance
- Isaac Lauer
- Nicolas Loubet
- et al.
- 2015
- VLSI Technology 2015
Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme
- Hsinyu Tsai
- Hiroyuki Miyazoe
- et al.
- 2014
- IEDM 2014
Contamination mitigation of hydrogen silsesquioxane resist processed with Na+-containing developer for nanoscale CMOS device patterning
- Markus Brink
- Isaac Lauer
- et al.
- 2014
- Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics
Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond
- Sarunya Bangsaruntip
- K. Balakrishnan
- et al.
- 2013
- IEDM 2013
Low-power circuit analysis and design based on heterojunction tunneling transistors (HETTs)
- Yoonmyung Lee
- Daeyeon Kim
- et al.
- 2013
- IEEE Transactions on VLSI Systems
Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications
- Hsin-Yu Tsai
- Hiroyuki Miyazoe
- et al.
- 2013
- SPIE Advanced Lithography 2013
Meeting the challenge of multiple threshold voltages in highly scaled undoped FinFETs
- Ramachandran Muralidhar
- Jin Cai
- et al.
- 2013
- IEEE T-ED
Channel doping impact on FinFETs for 22nm and beyond
- Chung-Hsun Lin
- R. Kambhampati
- et al.
- 2012
- VLSI Technology 2012