Experimental efficiency evaluation of stacked transistor half-bridge topologies in 14 nm cmos technology
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2021
- Electronics (Switzerland)
Publications
10 results for Johann Walter Kolar
Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration
- Thomas Brunschwiler
- Gerd Schlottig
- et al.
- 2017
- IEDM 2017
Analysis and comparative evaluation of stacked-Transistor half-bridge topologies implemented with 14 nm bulk CMOS technology
- Pedro André Martins Bezerra
- R.K. Aljameh
- et al.
- 2017
- COMPEL 2017
Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
A 10 W On-Chip Switched Capacitor Voltage Regulator with Feedforward Regulation Capability for Granular Microprocessor Power Delivery
- Toke M. Andersen
- Florian Krismer
- et al.
- 2017
- IEEE-TEPL
Modeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2015
- COBEP/SPEC 2015
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2015
- ISSCC 2015
A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2014
- APEC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- Toke Meyer Andersen
- Florian Krismer
- et al.
- 2014
- ISSCC 2014
A 4.6W/mm2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- Toke M. Andersen
- Florian Krismer
- et al.
- 2013
- APEC 2013