Experimental efficiency evaluation of stacked transistor half-bridge topologies in 14 nm cmos technology
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2021
- Electronics (Switzerland)
Paper
Publications
5 results for Pedro André Martins Bezerra
Towards cube-sized compute nodes: Advanced packaging concepts enabling extreme 3D integration
- Thomas Brunschwiler
- Gerd Schlottig
- et al.
- 2017
- IEDM 2017
Conference paperAnalysis and comparative evaluation of stacked-Transistor half-bridge topologies implemented with 14 nm bulk CMOS technology
- Pedro André Martins Bezerra
- R.K. Aljameh
- et al.
- 2017
- COMPEL 2017
Conference paperScalable packaging platform supporting high-performance 3D chip stacks
- Thomas Brunschwiler
- Gerd Schlottig
- et al.
- 2017
- Pan Pacific 2017
Conference paperModeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2015
- COBEP/SPEC 2015
Conference paper