A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
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182 results for Eduard Cartier
Voltage ramp stress based stress-and-sense test method for reliability characterization of Hf-base high-k/metal gate stacks for CMOS technologies
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- ECS Meeting 2011
Full metal gate with borderless contact for 14 nm and beyond
- Soon-Cheon Seo
- L.F. Edge
- et al.
- 2011
- VLSI Technology 2011
On the electron and hole tunneling in a HfO2 gate stack with extreme interfacial-layer scaling
- Takashi Ando
- Ninad D. Sathaye
- et al.
- 2011
- IEEE Electron Device Letters
A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS
- D.P. Ioannou
- K. Zhao
- et al.
- 2011
- IRPS 2011
PBTI under dynamic stress: From a single defect point of view
- K. Zhao
- J.H. Stathis
- et al.
- 2011
- IRPS 2011
Analysis of recoverable and non-recoverable NBTI and PBTI using AC and DC stresses
- Frederic Monsieur
- Eduard Cartier
- et al.
- 2011
- IRPS 2011
Fast characterization of the Static Noise Margin degradation of cross-coupled inverters and correlation to BTI instabilities in MG/HK devices
- Andreas Kerber
- N. Pimparkar
- et al.
- 2011
- IRPS 2011
High temperature (1000°C) compatible Y-La-Si-O silicate gate dielectric in direct contact with Si with 7.7 Å equivalent oxide thickness
- Catherine Dubourdieu
- E. Cartier
- et al.
- 2011
- Applied Physics Letters
Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs
- A. Kerber
- A. Vayshenker
- et al.
- 2010
- IRPS 2010