SiGe HBT technology with f max/f T = 350/300 GHz and gate delay below 3.3 ps
- M. Khater
- J.-S. Rieh
- et al.
- 2004
- IEDM 2004
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32 results for Jeffrey B. Johnson
SiGe HBTs for millimeter-wave applications with simultaneously optimized f T and f max of 300 GHz
- J.-S. Rieh
- D.R. Greenberg
- et al.
- 2004
- RFIC 2004
Integrated SiGe and Si device capabilities and trends for multi-gigahertz applications
- G. Freeman
- B. Jagannathan
- et al.
- 2003
- International Journal of High Speed Electronics and Systems
Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies
- David L. Harame
- Kim M. Newton
- et al.
- 2003
- IBM J. Res. Dev
A simulation study on thin SOI bipolar transistors with fully or partially depleted collector
- Qiqing Ouyang
- Jin Cai
- et al.
- 2002
- BCTM 2002
Self-aligned SiGe NPN transistors with 285 GHz f MAX and 207 GHz f T in a manufacturable technology
- B. Jagannathan
- M. Khater
- et al.
- 2002
- IEEE Electron Device Letters
0.18 um modular triple self-aligned embedded split-gate flash memory
- Rebecca Mih
- Jay Harrington
- et al.
- 2000
- Digest of Technical Papers-Symposium on VLSI Technology
Fowler-Nordheim tunneling of carriers in MOS transistors: Two-dimensional simulation of gate current employing FIELDAY
- S.N. Mohammad
- G. Fiorenza
- et al.
- 1995
- Solid State Electronics
SiGe-Channel Heterojunction p-MOSFET’s
- Sophie Verdonckt-Vandebroek
- Bernard S. Meyerson
- et al.
- 1994
- IEEE Transactions on Electron Devices
A room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993