Publications

2 results for Hayun Chung

A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
- - Hayun Chung
  - Zeynep Toprak-Deniz
  - et al.
- 2015
- Analog Integr Circuits Signal Process
A 7.5-GS/s 3.8-ENOB 52-mW flash ADC with clock duty cycle control in 65nm CMOS
- - Hayun Chung
  - Alexander Rylyakov
  - et al.
- 2009
- VLSI Circuits 2009