Breakdown data generation and in-die deconvolution methodology to address BEOL and MOL dielectric breakdown challengesF. ChenCarole Graaset al.2015Microelectronics Reliability
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate processW. McMahonC. Tianet al.2013IRPS 2013
High performance bulk planar 20nm CMOS technology for low power mobile applicationsHuiling ShangSameer Jainet al.2012VLSI Technology 2012
High performance transistors featured in an aggressively scaled 45nm bulk CMOS technologyZ. LuoN. Rovedoet al.2007VLSI Technology 2007
Reliability investigation of NiPtSi electrical fuse with different programming mechanismsC. TianD. Moyet al.2007IIRW 2007
Reliability qualification of CoSI2 electrical fuse for 90NM technologyC. TianB. Parket al.2006IRPS 2006
A 45 nm CMOS node Cu/low-k/ ULtra low-k PECVD SiCOH (k=2.4) BEOL technologyS. SankaranS. Araiet al.2006IEDM 2006
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithographyS. NarasimhaK. Onishiet al.2006IEDM 2006