A 35mW8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32nm Digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- VLSI Circuits 2013
Conference paper
Publications
54 results for Martin L. Schmatz
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS
- Lukas Kull
- Thomas Toifl
- et al.
- 2013
- ISSCC 2013
Conference paperA 4.5 mW/Gb/s 6.4 Gb/s 22+1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS
- Robert Reutemann
- Michael Ruegg
- et al.
- 2010
- IEEE Journal of Solid-State Circuits
PaperAntenna coupled far-infrared/THz detector in CMOS
- T. Morf
- Jonas Weiss
- et al.
- 2009
- Electronics Letters
PaperA 1.255 GHz clock generator with high-bandwidth supply-rejection using a regulated-replica regulator in 45-nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
PaperSwitched inductor with wide tuning range and small inductance step sizes
- Marcel Kossel
- Thomas Morf
- et al.
- 2009
- IEEE MWCL
PaperA 5.75 to 44 Gb/s quarter rate CDR with data rate selection in 90 nm bulk CMOS
- Lucio Rodoni
- George Von Büren
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
PaperLC PLL with 1.2-octave locking range based on mutual-inductance switching in 45-nm SOI CMOS
- Marcel Kossel
- Thomas Morf
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
Paper5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS
- George Von Bueren
- Lucio Rodoni
- et al.
- 2008
- ESSCIRC 2008
Conference paperA T-coil-enhanced 8.5 Gb/s high-swing SST transmitter in 65 nm bulk CMOS with < 16 dB return loss over 10 GHz bandwidth
- Marcel Kossel
- Christian Menolfi
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Paper