Publications

3 results for Giovanni Cervelli

A 28.05Gb/s transceiver using quarter-rate triple-speculation hybrid-DFE receiver with calibrated sampling phases in 32nm CMOS
- - Gautam Gangasani
  - John F. Bulzacchelli
  - et al.
- 2017
- VLSI Circuits 2017
A 32 Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32 nm SOI CMOS technology
- - Gautam R. Gangasani
  - Chun-Ming Hsu
  - et al.
- 2014
- IEEE JSSC
A 32-Gb/s backplane transceiver with on-chip AC-coupling and low latency CDR in 32-nm SOI CMOS technology
- - Gautam R. Gangasani
  - John F. Bulzacchelli
  - et al.
- 2013
- A-SSCC 2013