Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
- Ishita Jain
- Anshul Gupta
- et al.
- 2018
- IEEE T-ED
Paper
Publications
4 results for Ishita Jain
Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET
- Ishita Jain
- Anshul Gupta
- et al.
- 2016
- ICEE 2016
Conference paperSeries resistance reduction in stacked nanowire FETs for 7-nm CMOS technology
- Anil K. Bansal
- Ishita Jain
- et al.
- 2016
- IEEE J-EDS
PaperNanowire FET design for 7-nm SOI-CMOS technology
- Ishita Jain
- Anil K. Bansal
- et al.
- 2015
- S3S 2015
Conference paper