Optimal dual-VT design in sub-100 nanometer PDSOI and double-gate technologies
- Aditya Bansal
- Jae-Joon Kim
- et al.
- 2008
- VLSID 2008
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46 results for Jae-Joon Kim
High-performance device optimization and dual-VT technology options for doublegate FET
- Aditya Bansal
- Keunwoo Kim
- et al.
- 2007
- ICICDT 2007
Evaluation and optimization of FinFET quantization error in porting a design from planar silicon technology
- R.M. Rao
- J. Kim
- et al.
- 2007
- SOI 2007
Accurate modeling and analysis of currents in trapezoidal FinFET devices
- R.M. Rao
- A. Bansal
- et al.
- 2007
- SOI 2007
High-performance SRAM in nanoscale CMOS: Design challenges and techniques
- Ching-Te Chuang
- Saibal Mukhopadhyay
- et al.
- 2007
- MTDT 2007
Asymmetrical SRAM cells with enhanced read and write margins
- Keunwoo Kim
- Jae-Joon Kim
- et al.
- 2007
- VLSI-TSA 2007
Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
- Jae-Joon Kim
- Keunwoo Kim
- et al.
- 2006
- ESSCIRC 2006
Robust level converter design for sub-threshold logic
- Ik Joon Chang
- Jae-Joon Kim
- et al.
- 2006
- ISLPED 2006
Independent-gate controlled asymmetrical SRAM cells in double-gate MOSFET technology for improved READ stability
- Jae-Joon Kim
- Keunwoo Kim
- et al.
- 2006
- ESSDERC 2006
Modeling and analysis of gate leakage in ultra-thin oxide sub-50nm double gate devices and circuits
- Saibal Mukhopadhyay
- Keunwoo Kim
- et al.
- 2005
- ISQED 2005