Soft error rate scaling for emerging SOI technology options
- P. Oldiges
- K. Bernstein
- et al.
- 2002
- VLSI Technology 2002
Conference paper
Publications
80 results for Robert Dennard
Supply voltage strategies for minimizing the power of CMOS processors
- Jin Cai
- Yuan Taur
- et al.
- 2002
- VLSI Technology 2002
Conference paperChallenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev
ReviewScalability and biasing strategy for CMOS with active well bias
- S. Huang
- C. Wann
- et al.
- 2001
- VLSI Technology 2001
Conference paperDevice scaling limits of Si MOSFETs and their application dependencies
- David J. Frank
- Robert H. Dennard
- et al.
- 2001
- Proceedings of the IEEE
PaperTheoretical determination of the temporal and spatial structure of α-particle induced electron-hole pair generation in silicon
- Phil Oldiges
- Robert Dennard
- et al.
- 2000
- IEEE TNS
Paper1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro
- O. Takahashi
- S. Dhong
- et al.
- 2000
- ISSCC 2000
Conference paper1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro
- Osamu Takahashi
- Sang H. Dhong
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
PaperCMOS with active well bias for low-power and RF/analog applications
- Clement Wann
- Jay Harrington
- et al.
- 2000
- Digest of Technical Papers-Symposium on VLSI Technology
PaperWhen are transmission-line effects important for on-chip interconnections?
- Alina Deutsch
- Gerard V. Kopcsay
- et al.
- 1997
- IEEE T-MTT
Paper