Publications

22 results for Michael Belyansky

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- - H.S. Yang
  - R. Malik
  - et al.
- 2004
- IEDM 2004