Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
Publications
2 results for Ghavam Shahidi
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
- Shay Reboh
- Chen Zhang
- et al.
- 2025
- VLSI Technology and Circuits 2025