Novel approach to reduce source/drain series resistance in high performance CMOS devices using self-aligned CoWP process for 45nm node UTSOI transistors with 20nm gate length
- James Pan
- Anna Topol
- et al.
- 2006
- VLSI Technology 2006
Publications
Date
Featured collections
Popular topics
29 results for Anna Topol
Lower resistance scaled metal contacts to silicide for advanced CMOS
- A. Topol
- C. Sheraw
- et al.
- 2006
- VLSI Technology 2006
Critical aspects of layer transfer and alignment tolerances for 3D integration processes
- D.C. La Tulipe
- L.T. Shi
- et al.
- 2006
- GBC 2006
Structure, design and process control for Cu bonded interconnects in 3D integrated circuits
- Kuan-Neng Chen
- Sang Hwui Lee
- et al.
- 2006
- IEDM 2006
3D integrated circuits and silicon carrier packaging realization
- Cornelia K. Tsang
- Anna W. Topol
- 2006
- VMIC 2006
Improved manufacturability of Cu bond pads and implementation of seal design in 3D integrated circuits and packages
- K.N. Chen
- C. Tsang
- et al.
- 2006
- VMIC 2006
Three-dimensional integrated circuits
- Anna W. Topol
- Douglas C. La Tulipe Jr.
- et al.
- 2006
- IBM J. Res. Dev
Transistor scaling with novel materials
- Meikei Ieong
- Vijay Narayanan
- et al.
- 2006
- Materials Today
Hybrid lithography: The marriage between optical and e-beam lithography. A method to study process integration and device performance for advanced device nodes
- Steven Steen
- Sharee J. McNab
- et al.
- 2006
- Microelectronic Engineering
Mobility and CMOS devices/circuits on sub-10nm (110) ultra thin body SOI
- Huiling Shang
- J. Rubino
- et al.
- 2005
- VLSI Technology 2005