Copper-filled through wafer vias with very low inductance
- Keith A. Jenkins
- Chirag S. Patel
- 2005
- IITC 2005
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235 results for Keith A. Jenkins
Characterization of flip chip microjoins up to 40 GHz using silicon carrier
- Chirag S. Patel
- Paul S. Andry
- et al.
- 2005
- IITC 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- E. Leobandung
- H. Nayakama
- et al.
- 2005
- VLSI Technology 2005
On-chip spectrum analyzer for analog built-in self test
- Anup P. Jose
- Keith A. Jenkins
- et al.
- 2005
- VTS 2005
An on-chip jitter measurement circuit with sub-picosecond resolution
- Keith A. Jenkins
- Anup P. Jose
- et al.
- 2005
- ESSCIRC 2005
Circuit to measure high speed pulse I-V characteristics with only DC I/O's
- Mark B. Ketchen
- Manjul Bhushan
- et al.
- 2005
- IEEE International SOI Conference 2005
Assembly technology for three dimensional integrated circuits
- A. Topol
- D.C. La Tulipe
- et al.
- 2005
- VMIC 2005
A circuit-sensitive methodology for evaluating substrate noise
- John Liobe
- Keith A. Jenkins
- 2005
- RFIC 2005
Delay chain based programmable jitt+er generator
- Tian Xia
- Peilin Song
- et al.
- 2004
- ETS 2004
Substrate coupling noise issues in silicon technology
- Keith A. Jenkins
- 2004
- SiRF 2004