High frequency input isolation circuit for asynchronous CMOS macros in PD/SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- IEEE International SOI Conference 2000
Publications
216 results for Rajiv V. Joshi
Controlling floating-body effects for 0.13μm and 0.10μm SOI CMOS
- S.K.H. Fung
- N. Zamdmer
- et al.
- 2000
- IEDM 2000
`Cool low power' 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology
- R.V. Joshi
- W. Hwang
- et al.
- 2000
- ISLPED 2000
2 GHz cycle, 430 ps access time 34 Kb L1 directory SRAM in 1.5 V, 0.18 μm CMOS bulk technology
- R.V. Joshi
- S.P. Kowalczyk
- et al.
- 2000
- VLSI Circuits 2000
Scannable pulse-to-static conversion register array for self-timed circuits
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Frequency dependent behavior of a high performance dynamic register file in 1.8 V, 0.25 μm SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- IEEE International SOI Conference 1999
Design considerations and implementations of a high performance dynamic register file
- R.V. Joshi
- W. Hwang
- 1999
- VLSID 1999
A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file
- Wei Hwang
- Rajiv V. Joshi
- et al.
- 1999
- IEEE Journal of Solid-State Circuits
Implementation of a high speed multiport register file in a 1.8V, 0.25 μm CMOS bulk and SOI technology
- R.V. Joshi
- W. Hwang
- et al.
- 1999
- International Symposium on VLSI Technology, Systems, and Applications, Proceedings
Designing a testable System on a Chip
- S.V. Kosonocky
- A.A. Bright
- et al.
- 1998
- VTS 1998