Publications

19 results for J. Strane

SOI FinFET versus bulk FinFET for 10nm and below
- - Terence B. Hook
  - F. Allibert
  - et al.
- 2014
- S3S 2014
10nm FINFET technology for low power and high performance applications
- - D. Guo
  - H. Shang
  - et al.
- 2014
- ICSICT 2014
High performance bulk planar 20nm CMOS technology for low power mobile applications
- - Huiling Shang
  - Sameer Jain
  - et al.
- 2012
- VLSI Technology 2012
Optimizing stressor film deposition sequence in polish rate order for best planarization
- - John H. Zhang
  - Changyong Xiao
  - et al.
- 2011
- MRS Spring Meeting 2011
Comparative study of CVD TiN vs. ALD TiN for contact metallization in 32nm node and beyond
- - Valli Arunachalam
  - Filippos Papadatos
  - et al.
- 2010
- ADMETA 2010
Extending dual stress liner process to high performance 32nm node SOI CMOS manufacturing
- - M. Cai
  - B. Greene
  - et al.
- 2008
- IEEE International SOI Conference 2008
Ni-Pt silicide formation through Ti mediating layers
- - Paul Besser
  - Christian Lavoie
  - et al.
- 2007
- Microelectronic Engineering
Implementation of robust nickel alloy salicide process for high-performance 65nm SOI CMOS manufacturing
- - Jay Strane
  - David Brown
  - et al.
- 2007
- VLSI-TSA 2007
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005