A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
Publications
3 results for Hartmud Terletzki
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
- Toshiaki Kirihata
- Martin Gall
- et al.
- 1998
- IEEE Journal of Solid-State Circuits
220 mm2 4 and 8 bank 256 Mb SDRAM with single-sided stitched WL architecture
- T. Kirihata
- M. Gall
- et al.
- 1998
- ISSCC 1998