Novel circuits to improve SRAM performance in PD/SOI technology
- R.V. Joshi
- A.J. Bhavnagarwala
- et al.
- 2001
- IEEE International SOI Conference 2001
Publications
6 results for Louis Lu-Chen Hsu
A 7F2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAM's
- Heinz Hoenigschmid
- Alexander Frey
- et al.
- 2000
- IEEE Journal of Solid-State Circuits
SOI MOSFET mismatch due to floating-body effects
- J.A. Mandelman
- F. Assaderaghi
- et al.
- 1997
- IEEE International SOI Conference 1997
Floating-body effects in partially depleted SOI CMOS circuits
- Pong-Fei Lu
- Ching-Te Chuang
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
Floating body effects in partially-depleted SOI CMOS circuits
- P.F. Lu
- J. Ji
- et al.
- 1996
- LPED 1996
Floating body effects in partially-depleted SOI CMOS circuits
- P.F. Lu
- J. Ji
- et al.
- 1996
- LPED 1996