Logic Gates as Repeaters (LGR) for area-efficient timing optimization
- Michael Moreinis
- Arkadiy Morgenshtein
- et al.
- 2006
- IEEE Transactions on VLSI Systems
Paper
Publications
4 results for Avinoam Kolodny
Simple design criterion for maximizing data rate in NoC links
- Anastasia Barger
- David Goren
- et al.
- 2006
- IEEE-SPI 2006
Conference paperDesign and modelling of network on chip interconnects using transmission lines
- Anastasia Barger
- David Goren
- et al.
- 2004
- ICECS 2004
Conference paperRepeater Insertion combined with LGR methodology for on-chip interconnect timing optimization
- Michael Moreinis
- Arkadiy Morgenshtein
- et al.
- 2004
- ICECS 2004
Conference paper