A 2-GHz direct sampling delta-sigma tunable receiver with 40-GHz sampling clock and on-chip PLL
- T. Chalvatzis
- T.O. Dickson
- et al.
- 2007
- VLSI Circuits 2007
Conference paper
Publications
2 results for T. Chalvatzis
Towards a sub-2.5V, 100-Gb/s Serial Transceiver
- S.P. Voinigescu
- R. Aroca
- et al.
- 2007
- CICC 2007
Conference paper