A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- Peter Klim
- John Barth
- et al.
- 2008
- VLSI Circuits 2008
Conference paper
Publications
5 results for J.B. Kuang
Gate leakage effects on yield and design considerations of PD/SOI SRAM designs
- Rouwaida Kanj
- Rajiv Joshi
- et al.
- 2007
- ISQED 2007
Conference paperThe design and implementation of a low-overhead supply-gated SRAM
- J.B. Kuang
- Hung Ngo
- et al.
- 2006
- ESSCIRC 2006
Conference paperAn asymmetrical double-gate VCO with wide frequency range
- Hung Ngo
- Keunwoo Kim
- et al.
- 2006
- VLSI-TSA 2006
Conference paperA floating-body charge monitoring technique for partially depleted SOI technology
- J.B. Kuang
- M.J. Saccamango
- et al.
- 2004
- International Journal of Electronics
Paper