Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs beyond 7nm
- Heng Wu
- Oleg Gluschenkov
- et al.
- 2018
- IEDM 2018
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10 results for Stan Tsai
Integrated dual SPE processes with low contact resistivity for future CMOS technologies
- Heng Wu
- Soon-Cheon Seo
- et al.
- 2017
- IEDM 2017
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
- Ruilong Xie
- Pietro Montanini
- et al.
- 2016
- IEDM 2016
Air spacer for 10nm FinFET CMOS and beyond
- K. Cheng
- C. Park
- et al.
- 2016
- IEDM 2016
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Gas cluster ion beam processing for improved self aligned contact yield at 7 nm node FinFET: MJ: MOL and junction interfaces
- Su Chen Fan
- Sean Teehan
- et al.
- 2018
- ASMC 2018
CMP: Consideration of stop-on selectivity in advanced node semiconductor manufacturing technology
- Stan Tsai
- Hari Amanapu
- et al.
- 2017
- ECS Meeting 2017 - New Orleans
Tungsten and cobalt metallization: A material study for MOL local interconnects
- Vimal Kamineni
- Mark Raymond
- et al.
- 2016
- IITC/AMC 2016
Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology
- L. Economikos
- X. Wang
- et al.
- 2004
- IITC 2004
CMP Challenges for Advanced Technology Nodes
- John H Zhang
- Haigou Huang
- et al.
- 2017
- MRS Advances