A resonant global clock distribution for the cell broadband engine processor
- Steven C. Chan
- Phillip J. Restle
- et al.
- 2009
- IEEE Journal of Solid-State Circuits
Paper
Publications
8 results for J. Keaty
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
- Dac Pham
- Hans-Werner Anderson
- et al.
- 2006
- ASP-DAC 2006
Conference paperOverview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- D.C. Pham
- T. Aipperspach
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
PaperThe design and implementation of a first-generation CELL processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
Conference paperThe design and implementation of a first-generation CELL Processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
Conference paperThe design methodology and implementation of a first-generation CELL processor: A multi-core SoC
- D.C. Pham
- E. Behnen
- et al.
- 2005
- CICC 2005
Conference paperThe design and implementation of a first-generation CELL processor - A multi-core SoC
- D.C. Pham
- S. Asano
- et al.
- 2005
- ICICDT 2005
Conference paperThe circuit and physical design of the POWER4 microprocessor
- J. Warnock
- J. Keaty
- et al.
- 2002
- IBM J. Res. Dev
Paper