A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- Troy Beukema
- Michael Sorna
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
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14 results for Woogeun Rhee
A Semi-Digital Delay-Locked Loop Using an Analog-Based Finite State Machine
- Woogeun Rhee
- Benjamin Parker
- et al.
- 2004
- IEEE TCAS-II
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with < 10-Hz RF carrier resolution
- Woogeun Rhee
- Biagio Bisanti
- et al.
- 2002
- IEEE Journal of Solid-State Circuits