Pb-free micro-joints (50 μm pitch) for the next generation micro-systems: The fabrication, assembly and characterization
- H. Gan
- S.L. Wright
- et al.
- 2006
- ECTC 2006
Conference paper
Publications
24 results for Raymond Horton
A CMOS-compatible process for fabricating electrical through-vias in silicon
- P. Andry
- C. Tsang
- et al.
- 2006
- ECTC 2006
Conference paperSystem-on-Package (SOP) technology, characterization and applications
- J. Knickerbocker
- P. Andry
- et al.
- 2006
- ECTC 2006
Conference paperCharacterization of micro-bump C4 interconnects for Si-carrier SOP applications
- S.L. Wright
- R.J. Polastre
- et al.
- 2006
- ECTC 2006
Conference paper3-D silicon integration and silicon packaging technology using silicon through-vias
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
PaperSilicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ADMETA 2005
Conference paperCharacterization of flip chip microjoins up to 40 GHz using silicon carrier
- Chirag S. Patel
- Paul S. Andry
- et al.
- 2005
- IITC 2005
Conference paperSilicon carrier with deep through-vias, fine pitch wiring, and through cavity for parallel optical transceiver
- Chirag S. Patel
- Cornelia K. Tsang
- et al.
- 2005
- ECTC 2005
Conference paperThree dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology
- John U. Knickerbocker
- Chirag S. Patel
- et al.
- 2005
- CICC 2005
Conference paperDevelopment of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection
- John U. Knickerbocker
- Paul S. Andry
- et al.
- 2005
- IBM J. Res. Dev
Paper