Publications

3 results for M. Gerhardt

Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies
- - M. Horstmann
  - A. Wei
  - et al.
- 2005
- IEDM 2005
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
- - E. Leobandung
  - H. Nayakama
  - et al.
- 2005
- VLSI Technology 2005
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
- - H.S. Yang
  - R. Malik
  - et al.
- 2004
- IEDM 2004