A 45nm low cost low power platform by using integrated dual-stress-liner technology
- J. Yuan
- S.S. Tan
- et al.
- 2006
- VLSI Technology 2006
Conference paper
Publications
9 results for R.S. Amos
Stress proximity technique for performance improvement with dual stress liner at 45nm technology and beyond
- X. Chen
- S. Fang
- et al.
- 2006
- VLSI Technology 2006
Conference paperNovel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices
- J.-P. Han
- H. Utomo
- et al.
- 2006
- IEDM 2006
Conference paperProcess induced stress for CMOS performance improvement
- S. Fang
- S.S. Tan
- et al.
- 2006
- ICSICT 2006
Conference paperDesign of high performance PFETs with strained Si channel and laser anneal
- Z. Luo
- Y.F. Chong
- et al.
- 2005
- IEDM 2005
Conference paperEvaluation of thermal stability for CMOS gate metal materials
- C. Cabral Jr.
- C. Lavoie
- et al.
- 2004
- JES
PaperAdvanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- E. Gusev
- C. Cabral Jr.
- et al.
- 2004
- IEDM 2004
Conference paperMetal-gate FinFET and fully-depleted SOI devices using total gate silicidation
- Jakub Kedzierski
- Edward Nowak
- et al.
- 2002
- IEDM 2002
Conference paperA method for measuring barrier heights, metal work functions and fixed charge densities in metal/SiO2/Si capacitors
- Sufi Zafar
- Cyril Cabral Jr.
- et al.
- 2002
- Applied Physics Letters
Paper