Publications

5 results for Jaganathan Narasimhan

Maze routing steiner trees with delay versus wire length tradeoff
- - Renato Hentschke
  - Jaganathan Narasimhan
  - et al.
- 2009
- IEEE Transactions on VLSI Systems
Maze routing steiner trees with effective critical sink optimization
- - Renato F. Hentschke
  - Jaganathan Narasimham
  - et al.
- 2007
- ISPD 2007
Improving run times by pruned application of synthesis transforms
- - Renato F. Hentschke
  - Jagannathan Narasimhan
  - et al.
- 2005
- SBCCI 2005
A graph theoretical approach for the yield enhancement of reconfigurable VLSI/WSI arrays
- - Jagannathan Narasimhan
  - Kazuo Nakajima
  - et al.
- 1999
- Discrete Applied Mathematics
Yield Enhancement of Programmable ASIC Arrays by Reconfiguration of Circuit Placements
- - J. Narasimhan
  - K. Nakajima
  - et al.
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems