Evaluation of Cu wiring in a production 64 Mb DRAM
- W. Cote
- G. Costrini
- et al.
- 1998
- VLSI Technology 1998
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23 results for Gary Bronner
Evaluation of X-ray lithography using a 0.175 μm (0.245 μm2 cell area) 1 Gb DRAM technology
- Rosemary Longo
- S. Chaloux
- et al.
- 1998
- VLSI Technology 1998
0.21 μm2 7F2 trench cell with a locally-open globally-folded dual bitline for 1 Gb/4 Gb DRAM
- C. Radens
- U. Gruening
- et al.
- 1998
- VLSI Technology 1998
DRAM technologies for today's market and future DRAM generations
- W. Neumueller
- J. Alsmeier
- et al.
- 1997
- ESSDERC 1997
Characteristics of vertical p-channel MOSFETs for high density circuit application
- D.S. Wen
- W.H. Chang
- et al.
- 1991
- VLSI-TSA 1991
Experimental 27 ns 1 Mb CMOS high-speed DRAM
- S. Dhong
- W.H. Henkels
- et al.
- 1989
- VLSI Circuits 1989
Fully self-aligned epitaxial-base transistor
- R. Schulz
- M. Jost
- et al.
- 1989
- VLSI Technology 1989
Gettering of metal precipitates
- Gary Bronner
- James Plummer
- 1987
- ESSDERC 1987
Optimization of silicon technology for the IBM System z9
- Daniel J. Poindexter
- Scott R. Stiffler
- et al.
- 2007
- IBM J. Res. Dev
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
- Jack A. Mandelman
- Robert H. Dennard
- et al.
- 2002
- IBM J. Res. Dev