A 60 Gb/s 1.9 pJ/bit NRZ optical-receiver with low latency digital CDR in 14nm CMOS FinFET
- Alessandro Cevrero
- Ilter Ozkaya
- et al.
- 2017
- VLSI Circuits 2017
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95 results for Thomas Toifl
A 5Gb/s 7.1fJ/b/mm 8× multi-drop on-chip 10mm data link in 14nm FinFET CMOS SOI at 0.5V
- Elisa Sacco
- Pier Andrea Francese
- et al.
- 2017
- VLSI Circuits 2017
A 12b 61dB SNDR 300MS/s SAR ADC with inverter-based preamplifier and common-mode-regulation DAC in 14nm CMOS FinFET
- Danny Luu
- Lukas Kull
- et al.
- 2017
- VLSI Circuits 2017
Design considerations on sliding-block viterbi detectors for high-speed data transmission
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- ICSPCS 2016
High-speed link with trellis-coded modulation and Reed-Solomon coding
- Hazar Yueksel
- Giovanni Cherubini
- et al.
- 2016
- CSCN 2016
Exploration of inductor-based hybrid integrated voltage regulator architectures
- Arvind Sridhar
- Thomas Brunschwiler
- et al.
- 2016
- ESTC 2016
CMOS ADCs Towards 100 GS/s and beyond
- Lukas Kull
- Danny Luu
- et al.
- 2016
- CSICS 2016
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
- Hazar Yueksel
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Design considerations for 50G+ backplane links
- Thomas Toifl
- Matthias Braendli
- et al.
- 2016
- ESSCIRC 2016
Modeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications
- Pedro André Martins Bezerra
- Florian Krismer
- et al.
- 2015
- COBEP/SPEC 2015