Publications

95 results for Thomas Toifl

A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- - Sergey V. Rylov
  - Troy Beukema
  - et al.
- 2016
- ISSCC 2016
Modeling and multi-objective optimization of 2.5D inductor-based Fully Integrated Voltage Regulators for microprocessor applications
- - Pedro André Martins Bezerra
  - Florian Krismer
  - et al.
- 2015
- COBEP/SPEC 2015
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- - Hazar Yueksel
  - Lukas Kull
  - et al.
- 2015
- ESSCIRC 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
- - Alessandro Cevrero
  - Cosimo Aprile
  - et al.
- 2015
- VLSI Circuits 2015
Adaptive optical interconnects: The ADDAPT project
- - Ronny Henker
  - J. Pliva
  - et al.
- 2015
- SPIE Optics + Photonics 2015
A feedforward controlled on-chip switched-capacitor voltage regulator delivering 10W in 32nm SOI CMOS
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2015
- ISSCC 2015
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm² in 32 nm SOI CMOS
- - Lukas Kull
  - J. Pliva
  - et al.
- 2014
- A-SSCC 2014
A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- IEEE JSSC
A DDR3/4 memory link TX supporting 24-40 ω, 0.8-1.6 V, 0.8-5.0 Gb/s with slew rate control and thin oxide output stages in 22-nm CMOS SOI
- - Marcel Kossel
  - Christian Menolfi
  - et al.
- 2014
- ESSCIRC 2014
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
- - Thomas Toifl
  - Peter Buchmann
  - et al.
- 2014
- ESSCIRC 2014