A mask reuse methodology for reducing system-on-a-chip cost
- Subhrajit Bhattacharya
- John Darringer
- et al.
- 2005
- ISQED 2005
Publications
6 results for Daniel L. Ostapko
Are on-chip power-ground planes really needed? A signal integrity perspective
- I.M. Elfadel
- Peter Feldmann
- et al.
- 2004
- IEEE Topical Meeting EPEPS 2004
On the signal bounding problem in timing analysis
- Jin-Fuw Lee
- D.L. Ostapko
- et al.
- 2001
- IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Interactive design language: A unified approach to hardware simulation, synthesis and documentation
- L.I. Maissel
- D.L. Ostapko
- 1982
- DAC 1982
A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
- Se June Hong
- Daniel L. Ostapko
- 1981
- IEEE TC
Fault Analysis and Test Generation for Programmable Logic Arrays (PLA's)
- Daniel L. Ostapko
- June Hong Se
- 1979
- IEEE TC