Gal Badishi, Idit Keidar, et al.
IEEE TDSC
We consider the problem of implementing a wait-free regular register from storage components prone to Byzantine faults. We present a simple, efficient, and self-contained construction of such a register. Our construction utilizes a novel building block, called a 1-regular register, which can be efficiently implemented from Byzantine fault-prone components. © 2006 Elsevier B.V. All rights reserved.
Gal Badishi, Idit Keidar, et al.
IEEE TDSC
B. Wagle
EJOR
Daniel M. Bikel, Vittorio Castelli
ACL 2008
S.F. Fan, W.B. Yun, et al.
Proceedings of SPIE 1989