VLSI implementation of high-Throughput, low-energy, configurable MIMO detector

This work focuses on a multi-core VLSI implementation of a multiple-input multiple-output (MIMO) detector utilizing a sphere-decoding algorithm. A complex-domain node traversal algorithm that achieves similar performance results as that of an exhaustive-search algorithm where every node is checked and sorted is also described. A 4×4, 64-QAM hard-output detector utilizing this VLSI design occupies 98k gates, and achieves near-ML performance with an average throughput of 1.22 Gb/s and an energy/bit of 23 pJ/b on a nominal 1.2 V supply in a 0.13μm CMOS process. The hard-output design can be further expanded to provide soft-output capability, and achieves an average throughput of 0.65 Gb/s and reaches 10-5 BER at an SNR of 19.7 dB.