Abhijeet Paul, Andres Bryant, et al.
IEDM 2013
Paper
Vertical Slit FET at 7-nm Node and beyond
Abstract
This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high ΔVt/Vg2s, and competitive drive capability with respect to a reference FinFET of comparable dimensions..
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