Hierarchical global wiring for custom chip design
W.K. Luk, D.T. Tang, et al.
DAC 1986
Vanguard is a new physical design system which combines advantages of gate array and custom design methods to produce high-density chips on non-custom regular images. Vanguard physically partitions a chip into subchips which define macro boundaries and which contain not only macro circuitry and internal macro wires but also inter-macro connections and portions of connections which are part of the final chip design and lie within that region. Subchips are individually designed and then connected by abutment to assemble the chip. Vanguard has been used to design a 32-bit DCVS microprocessor comprising 13 macros, including a large register array.
W.K. Luk, D.T. Tang, et al.
DAC 1986
Erich P. Stuntebeck, John S. Davis II, et al.
HotMobile 2008
Raymond Wu, Jie Lu
ITA Conference 2007
Pradip Bose
VTS 1998