Maneesha Rupakula, Junrui Zhang, et al.
IEEE J-EDS
Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits. © 2011 Macmillan Publishers Limited. All rights reserved.
Maneesha Rupakula, Junrui Zhang, et al.
IEEE J-EDS
F. Menges, M. Dittberner, et al.
Applied Physics Letters
Noelia Vico Triviño, Philipp Staudinger, et al.
CSW 2019
Peter Nirmalraj, Damien Thompson, et al.
Scientific Reports