Daniel Brand, Vijay S. Iyengar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The usual block-oriented timing analysis for logic circuits does not take into account functional relations between signals. If functional relations are taken into consideration, it may be found that a long path is never activated. This results in more accurate delays. This paper compares three arrival time functions–A, B, and R. Each one of these arrival time functions provides a set of times when a given signal is valid. A is the arrival time as given by exhaustive simulation. B is the arrival time as calculated by a usual block-oriented algorithm. R is the arrival time introduced in this paper, which does functional analysis. This paper will show that B ⊑R ⊑ A. The first relation means that R is never more conservative thanB and whenever the containment is proper, R is an improvement over B. The second relation means that R is correct in the sense that it will never assert a signal to be valid when it is not valid according to the idea A. The paper includes experimental results showing how often R is an improvement over B. © 1988 IEEE
Daniel Brand, Vijay S. Iyengar
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
William H. Joyner, Louise H. Trevillyan, et al.
DAC 1986
Daniel Brand, William H. Joyner
IEEE Transactions on Communications
William C. Carter, William H. Joyner, et al.
DAC 1979