Saurabh Sant, Paulina Aguirre, et al.
IEEE T-ED
Paper
Three-dimensional monolithic integration of III-V and Si(Ge) FETs for hybrid CMOS and beyond
Abstract
Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.
Related
H.J. Park, L. Pirro, et al.
Solid-State Electronics
Conference paper
(Invited) bringing HI-Vs into CMOS: From materials to circuits
Lukas Czornomaz, Veeresh Deshpande, et al.
ECS Meeting 2017 - New Orleans
Veeresh Deshpande, V. Djara, et al.
ECS Meeting 2015 Phoenix