ON THE IMPURITY PROFILES OF DOWN SCALED BIPOLAR TRANSISTORS.
D.D. Tang, G.P. Li, et al.
IEDM 1985
This paper presents the design and the characteristics of a nonvolatile memory cell using giant magneto-resistance effects. Unlike other magnetic memory cells [1], the present cell design [2] exploits the full ΔR of the spin valve material. A dc voltage difference between the two cell states of 30 mV range has been realized on a cell stripe only 6-micron long, making it compatible with the high-speed sensing schemes presently employed in silicon RAMs. The cell switches states in sub-nanoseconds. Its performance/density is close to that of the static RAM cell. © 1995 IEEE
D.D. Tang, G.P. Li, et al.
IEDM 1985
J. Warnock, J.D. Cressler, et al.
IEDM 1991
G. Shahidi, J. Warnock, et al.
VLSI Technology 1992
V.S. Speriosu, M.M. Chen, et al.
IEEE Transactions on Magnetics