A compact low-power 3D I/O in 45nm CMOS
Yong Liu, Wing Luk, et al.
ISSCC 2012
The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. © 1963-2012 IEEE.
Yong Liu, Wing Luk, et al.
ISSCC 2012
Suyoung Bang, Jae-Sun Seo, et al.
IEEE JSSC
Irem Boybat, Manuel Le Gallo, et al.
NVMTS 2017
Vinay Joshi, Manuel Le Gallo, et al.
Nature Communications