Special series on harsh chips

Augusto Vega; Alper Buyuktosunoglu; Pradip Bose

doi:10.1109/MM.2014.102

IEEE Micro

Review

01 Nov 2014

Special series on harsh chips

Download paper

Abstract

This introduction to the special series discusses the emerging field of harsh-environment-capable chips, or harsh chips. It also introduces the first two Harsh Chips articles in the issue.

Conference paper

Microarchitectural techniques for power gating of execution units

Zhigang Hu, Alper Buyuktosunoglu, et al.

ISLPED 2004

Conference paper

Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach

Jingwen Leng, Alper Buyuktosunoglu, et al.

MICRO 2015

Conference paper

Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary

Amlan Ganguly, Partha Kundu, et al.

NOCS 2011

Paper

A Novel Technique for Efficient Parallel Implementation of a Classical Logic/ Fault Simulation Problem

Pradip Bose

IEEE TC

View all publications

Abstract

Related

Microarchitectural techniques for power gating of execution units

Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach

Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary

A Novel Technique for Efficient Parallel Implementation of a Classical Logic/ Fault Simulation Problem