FPGA-based coprocessor for text string extraction
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
A general theory for characterizing and then realizing algorithms in hardware is given. The physical process of computation is interpreted in terms of a graph in physical space and time, and then an embedding into this graph of another graph which characterizes data flow in particular algorithms is given. The types of the special class of computational structures called systolic arrays which can occur physically are completely described, and a technique is developed for mapping the graph of a particular systolic algorithm into a physical array. Examples illustrate the methodology. © 1984 Springer-Verlag.
N.K. Ratha, A.K. Jain, et al.
Workshop CAMP 2000
Alessandro Morari, Roberto Gioiosa, et al.
IPDPS 2011
Yun Mao, Hani Jamjoom, et al.
CoNEXT 2006
Thomas M. Cover
IEEE Trans. Inf. Theory