Jieying Luo, Lan Wei, et al.
IEEE T-ED
An increasing interest in submicrometer-scale electronic systems has prompted study of the achievable charge confinement in ultra-narrow inversion lines. This paper describes the modeling and resultant charge distributions obtained via semi-classical calculations for the silicon grating-gate field-effect transistor. Since the gate structure of this device is periodic, a relatively small simulation region with welldefined boundary conditions could be employed. Using a finite-element technique, the charge and electrostatic potential is calculated numerically and self-consistently, as a function of electrode biases. Results are presented for charge confinement both directly underneath and between grating electrodes, and an effective capacitance is extracted for the strongest confinement regime. © 1986 IEEE
Jieying Luo, Lan Wei, et al.
IEEE T-ED
C.A. Ross, M. Hwang, et al.
Physical Review B - CMMP
G. Shahidi, J. Warnock, et al.
VLSI Technology 1993
J. Woodall, Alan C. Warren, et al.
IEEE T-ED