Robust Power Management: Ensuring SDC-free Functionality in Real Systems

Silent data corruption (SDC) is a term that has created a specter of doubt and fear amongst the information community in recent years. A special issue of IEEE Micro on SDC is about to appear, and in that theme issue, a position paper has been accepted for publication[1]. In that paper, we focus our attention on the problem of power management and the need for vigilance in ensuring SDC-free functionality in future power-constrained processor systems. In this workshop paper, we provide an experience-based report on how to stress-test and characterize an aggressively power-managed processor (in both pre- and post-silicon settings) in order to ensure robust functionality.

[1] P. Bose, R. Bertran, A. Buyuktosunoglu, H. Jacobson, K. Swaminathan, M. Pflanz, C. F. Webb, T. Webel, C. Jacobi, "Robust Power Management: A Key Aspect of SDC-free Systems," inIEEE Micro, doi: 10.1109/MM.2025.3644998 (to appear in the special issue on SDC).