Replacing design rules in the VLSI design cycle

We make a case for the migration of Design Rule Check (DRC), the first step in the modern VLSI design process, to a model-based system. DRC uses a large set of rules to determine permitted designs. We argue that it is a legacy of the past: slow, labor intensive, ad-hoc, inaccurate and too restrictive. We envisage the replacement of DRC and printability simulation by a signal processing and machine learning-based approach for 22nm technology nodes and beyond. Such a process would produce fast, accurate, autonomous printability prediction for optical lithography. As such, we built a proof-of-concept demonstrator that can predict OPC problems using a trained classifier without the need to fall back on costly first-principle simulation. For one sample test site, and for the OPC Line Width error type OPC violation marker, the demonstrator obtained an Equal Error Rate of ca. 4%. © 2012 Copyright SPIE.